HD6417750RF240DV Datasheet, PDF (537/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 13 Bus State Controller (BSC)
When both areas 2 and 3 are set to the synchronous DRAM, auto-refreshing of area 2 is
performed subsequent to area 3.
RTCNT value
RTCOR-1
RTCNT cleared to 0 when
RTCNT = RTCOR
H'00000000
RTCSR.CKS2–0
= 000 ≠ 000
Refresh
request
External bus
Refresh request cleared
by start of refresh cycle
Auto-refresh cycle
Figure 13.39 Auto-Refresh Operation
CKIO
TRr1 TRr2 TRr3 TRr4 TRrw TRr5 Trc Trc Trc
Time
CSn
RD/WR
RAS
CASS
DQMn
D63–D0
BS
CKE
Figure 13.40 Synchronous DRAM Auto-Refresh Timing
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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