HD6417750RF240DV Datasheet, PDF (639/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 14 Direct Memory Access Controller (DMAC)
In the example shown in figure 14.20, DMAC transfer begins, at the earliest, four CKIO cycles
after the first sampling operation, and the second sampling operation begins one cycle after the
start of the first DMAC transfer bus cycle.
In single address mode, the DACK signal is output every DMAC transfer cycle.
In figure 14.22, with a 32-byte data size, 64-bit bus width, and SDRAM: row hit write, DMAC
transfer begins, at the earliest, six CKIO cycles after the first sampling operation. The second
sampling operation begins one cycle after DACK is asserted for the first DMAC transfer.
4. Burst Mode, Dual Address Mode, Edge Detection
In burst mode using dual address mode and edge detection, DREQ sampling is performed in
the first cycle only.
For example, in the case shown in figure 14.15, DMAC transfer begins, at the earliest, five
CKIO cycles after the first sampling operation. DMAC transfer then continues until the end of
the number of data transfers set in DMATCR. DREQ is not sampled during this time, and
therefore DRAK is output in the first cycle only.
In the case of dual address mode transfer initiated by an external request, the DACK signal can
be output in either the read cycle or the write cycle of the DMAC transfer according to the
specification of the AM bit in CHCR.
5. Burst Mode, Single Address Mode, Edge Detection
In burst mode using single address mode and edge detection, DREQ sampling is performed
only in the first cycle.
For example, in the case shown in figure 14.21, DMAC transfer begins, at the earliest, five
cycles after the first sampling operation. DMAC transfer then continues until the end of the
number of data transfers set in DMATCR. DREQ is not sampled during this time, and
therefore DRAK is output in the first cycle only.
In single address mode, the DACK signal is output every DMAC transfer cycle.
Suspension of DMA Transfer in Case of DREQ Level Detection
With DREQ level detection in burst mode or cycle steal mode, and in dual address mode or single
address mode, the external device for which DMA transfer is being executed can judge from the
rising edge of CKIO that DARK has been asserted, and suspend DMA transfer by negating
DREQ. In this case, the next DARK signal is not output.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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