HD6417750RF240DV Datasheet, PDF (1062/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 22 Electrical Characteristics
SH7750, SH7750S, SH7750R Group
Table 22.41 Peripheral Module Signal Timing (5)
HD6417750
VF128 (V)
*²
HD6417750
F167 (V)
*³
HD6417750
BP200M (V)
*⁴
Module Item
INTC
NMI pulse
width (high)
NMI pulse
width (low)
H-UDI
Input clock
cycle
Input clock
pulse width
(high)
Symbol
t
NMIH
t_NMIL
t
TCKcyc
Min
5
30
5
30
50
Max
—
—
—
—
—
t_TCKH
15 —
Min Max
5
—
30 —
5
—
30 —
50 —
15 —
Min Max Unit
5
—t
cyc
30 — ns
5
—
t_cyc
30 — ns
50 — ns
15 — ns
Figure
22.71 Normal or sleep mode
22.71 Standby mode
22.71 Normal or sleep mode
22.71 Standby mode
22.67
22.67
Input clock t
TCKL
pulse width
(low)
15 —
15 —
15 — ns
22.67
Input clock t
TCKr
rise time
Input clock fall t
TCKf
time
ASEBRK
setup time
t_ASEBRKS
ASEBRK
hold time
t
ASEBRKH
TDI/TMS
t_TDIS
setup time
— 10
— 10
10 —
10 —
15 —
— 10
— 10
10 —
10 —
15 —
— 10 ns
— 10 ns
10
—
t_cyc
10 — t
cyc
15 — ns
22.67
22.67
22.68
22.68
22.69
TDI/TMS hold t
TDIH
time
15 —
15 —
15 — ns
22.69
TDO delay t
TDO
time
0
10
0
10
0
10 ns
22.69
ASE-PINBRK t
PINBRK
pulse width
2
—
2
—
2
— Pcyc^*1 22.70
Notes: 1. Pcyc: P clock cycles
2. V_DDQ = 3.0 to 3.6 V, V_DD = 1.5 V, T_a = –20 to +75°C, C_L = 30 pF, PLL2 on
3. V_DDQ = 3.0 to 3.6 V, V_DD = 1.8 V, T_a = –20 to +75°C, C_L = 30 pF, PLL2 on
4. V_DDQ = 3.0 to 3.6 V, V_DD = 1.8 V, T_a = –20 to +75°C, C_L = 30 pF, PLL2 on
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013