HD6417750RF240DV Datasheet, PDF (533/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 13 Bus State Controller (BSC)
CKIO
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
Tpr Tpc Tr Trw Tc1 Tc2 Tc3 Tc4 Trwl Trwl Trwl
Row
Row
H/L
Row
H/L
Row
c1
D63–D0
(read)
BS
c1
c2
c3
c4
CKE
DACKn
(SA: IO → memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.37 Burst Write Timing (Different Row Addresses)
Pipelined Access: When the RASD bit is set to 1 in MCR, pipelined access is performed between
an access by the CPU and an access by the DMAC, or in the case of consecutive accesses by the
DMAC, to provide faster access to synchronous DRAM. As synchronous DRAM is internally
divided into two or four banks, after a READ or WRIT command is issued for one bank it is
possible to issue a PRE, ACTV, or other command during the CAS latency cycle or data latch
cycle, or during the data write cycle, and so shorten the access cycle.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 481 of 1076