HD6417750RF240DV Datasheet, PDF (896/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 19 Interrupt Controller (INTC)
SH7750, SH7750S, SH7750R Group
Program
execution state
Interrupt
No
generated?
Yes
(BL bit
in SR = 0) or No
(sleep or standby
mode)?
Yes
No
NMI?
Yes
NMIB in
No
ICR = 1 and
NMI?
Yes
Level 15
No
interrupt?
Yes
Level 14
No
Yes
IMASK* =
interrupt?
level 14 or
lower?
Yes
Level 1
No
Set interrupt source
in INTEVT
No _Yes
IMASK =
level 13 or
lower?
interrupt?
Yes
Save SR to SSR;
save PC to SPC
No _Yes
IMASK =
level 0?
No
Set BL, MD, RB bits
in SR to 1
Branch to exception
handler
Note: * IMASK: Interrupt mask bits in status register (SR)
Figure 19.3 Interrupt Operation Flowchart
Page 844 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013