HD6417750RF240DV Datasheet, PDF (655/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 14 Direct Memory Access Controller (DMAC)
14.5 On-Demand Data Transfer Mode (DDT Mode)
14.5.1 Operation
Setting the DDT bit to 1 in DMAOR causes a transition to on-demand data transfer mode (DDT
mode). In DDT mode, it is possible to specify direct single address mode transfer to channel 0 via
the data bus and DDT module, and simultaneously issue a transfer request, using the DBREQ,
BAVL, TR, TDACK, and ID [1:0] signals between an external device and the DMAC. Figure
14.23 shows a block diagram of the DMAC, DDT, BSC, and an external device (with DBREQ,
BAVL, TR, TDACK, ID [1:0], and D [63:0] = DTR pins).
DMAC
SAR0
DAR0
DMATCR0
CHCR0
DREQ0–3
ddtmode tdack id[1:0]
BSC
Data buffer
DDT
Data
buffer
Request
ddtmode ^controller
bavl
TR
BAVL
DBREQ
TDACK
ID[1:0]
Memory
DTR
External
device (with
DBREQ, BAVL,
TR, TDACK,
and ID [1:0])
FIFO or
memory
Figure 14.23 On-Demand Transfer Mode Block Diagram
For channels 0 to 3, after making the settings for normal DMA transfer using the CPU, a transfer
request can be issued from an external device using the DBREQ, BAVL, TR, TDACK, ID [1:0],
and D [63:0] = DTR signals (handshake protocol using the data bus). A transfer request can also
be issued simply by asserting TR, without using the external bus (handshake protocol without use
of the data bus). For channel 2, after making the DMA transfer settings in the normal way, a
transfer request can be issued directly from an external device (with DBREQ, BAVL, TR,
TDACK, ID [1:0], and D [63:0] = DTR pins) by asserting DBREQ and TR simultaneously.
Note: DTR format = Data transfer request format
In DDT mode, there is a choice of five modes for performing DMA transfer.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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