HD6417750RF240DV Datasheet, PDF (696/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 14 Direct Memory Access Controller (DMAC)
SH7750, SH7750S, SH7750R Group
Bit 3⎯Request Queue Clear (QCL): Writing a 1 to this bit clears the request queues of the
corresponding channel as well as any external requests that have already been accepted. This bit is
only functional when DMAOR.DDT = 1 and DMAOR.DBL = 1.
CHCR Bit 3
QCL
0
1
Description
This bit is always read as 0.
Writing a 0 to this bit is invalid.
(Initial value)
When DMAOR.DBL = 1, writing a 1 to this bit clears the request queues on the
DDT side and any external requests stored in the DMAC. The written value is
not retained.
Bit 2—Interrupt Enable (IE): When this bit is set to 1, an interrupt request (DMTE) is generated
after the number of data transfers specified in DMATCR (when TE = 1). For details of the
settings, see the description of the IE bit in section 14.2.4, DMA Channel Control Registers 0−3
(CHCR0−CHCR3).
Bit 1—Transfer End (TE): This bit is set to 1 after the number of transfers specified in
DMATCR. If the IE bit is set to 1 at this time, an interrupt request (DMTE) is generated.
If data transfer ends before TE is set to 1 (for example, due to an NMI interrupt, address error, or
clearing of the DE bit or the DME bit in DMAOR), the TE bit is not set to 1. When this bit is 1,
the transfer enabled state is not entered even if the DE bit is set to 1. For details of the settings, see
the description of the TE bit in section 14.2.4, DMA Channel Control Registers 0−3
(CHCR0−CHCR3).
Bit 0—DMAC Enable (DE): Enables operation of the corresponding channel. For details of the
settings, see the description of the DE bit in section 14.2.4, DMA Channel Control Registers 0−3
(CHCR0−CHCR3).
Page 644 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013