HD6417750RF240DV Datasheet, PDF (630/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 14 Direct Memory Access Controller (DMAC)
SH7750, SH7750S, SH7750R Group
CKIO
A28–A0
CSn
D63–D0
DACK
WE
Address output to external memory
space
Data output from external device
with DACK
DACK signal to external
device with DACK
WE signal to external memory space
(a) From external device with DACK to external memory space
CKIO
A28–A0
CSn
D63–D0
RD
DACK
Address output to external memory
space
Data output from external memory
space
RD signal to external memory space
DACK signal to external
device with DACK
(b) From external memory space to external device with DACK
Figure 14.6 DMA Transfer Timing in Single Address Mode
Dual Address Mode: Dual address mode is used to access both the transfer source and the
transfer destination by address. The transfer source and destination can be accessed by either on-
chip peripheral module or external address.
Even if the operand cache is used in RAM mode, the RAM cannot be set as the transfer source or
transfer destination.
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013