HD6417750RF240DV Datasheet, PDF (29/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Figures
Section 1 Overview
Figure 1.1 Block Diagram of SH7750/SH7750S/SH7750R Group Functions ............................... 9
Figure 1.2 Pin Arrangement (256-Pin BGA) ................................................................................ 10
Figure 1.3 Pin Arrangement (208-Pin QFP) ................................................................................. 11
Figure 1.4 Pin Arrangement (264-Pin CSP) ................................................................................. 12
Figure 1.5 Pin Arrangement (292-Pin BGA) ................................................................................ 13
Section 2 Programming Model
Figure 2.1 Data Formats ............................................................................................................... 53
Figure 2.2 CPU Register Configuration in Each Processor Mode................................................ 56
Figure 2.3 General Registers ........................................................................................................ 58
Figure 2.4 Floating-Point Registers .............................................................................................. 61
Figure 2.5 Data Formats In Memory ............................................................................................ 67
Figure 2.6 Processor State Transitions.......................................................................................... 68
Section 3 Memory Management Unit (MMU)
Figure 3.1 Role of the MMU ........................................................................................................ 73
Figure 3.2 MMU-Related Registers.............................................................................................. 75
Figure 3.3 Physical Address Space (MMUCR.AT = 0) ............................................................... 79
Figure 3.4 P4 Area........................................................................................................................ 81
Figure 3.5 External Memory Space .............................................................................................. 82
Figure 3.6 Virtual Address Space (MMUCR.AT = 1).................................................................. 83
Figure 3.7 UTLB Configuration ................................................................................................... 86
Figure 3.8 Relationship between Page Size and Address Format................................................. 87
Figure 3.9 ITLB Configuration..................................................................................................... 90
Figure 3.10 Flowchart of Memory Access Using UTLB.............................................................. 91
Figure 3.11 Flowchart of Memory Access Using ITLB ............................................................... 92
Figure 3.12 Operation of LDTLB Instruction............................................................................... 94
Figure 3.13 Memory-Mapped ITLB Address Array................................................................... 103
Figure 3.14 Memory-Mapped ITLB Data Array 1 ..................................................................... 104
Figure 3.15 Memory-Mapped ITLB Data Array 2 ..................................................................... 105
Figure 3.16 Memory-Mapped UTLB Address Array ................................................................. 107
Figure 3.17 Memory-Mapped UTLB Data Array 1.................................................................... 108
Figure 3.18 Memory-Mapped UTLB Data Array 2.................................................................... 109
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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