HD6417750RF240DV Datasheet, PDF (830/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 17 Smart Card Interface
SH7750, SH7750S, SH7750R Group
17.2 Register Descriptions
Only registers that have been added, and bit functions that have been modified, for the smart card
interface are described here.
17.2.1 Smart Card Mode Register (SCSCMR1)
SCSCMR1 is an 8-bit readable/writable register that selects the smart card interface function.
SCSCMR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the
module standby state.
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
SDIR SINV
—
SMIF
Initial value: —
—
—
—
0
0
—
0
R/W: —
—
—
—
R/W R/W
—
R/W
Bits 7 to 4 and 1—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion
format.
Bit 3: SDIR
0
1
Description
SCTDR1 contents are transmitted LSB-first
Receive data is stored in SCRDR1 LSB-first
SCTDR1 contents are transmitted MSB-first
Receive data is stored in SCRDR1 MSB-first
(Initial value)
Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This
function is used together with the bit 3 function for communication with an inverse convention
card. The SINV bit does not affect the logic level of the parity bit. For parity-related setting
procedures, see section 17.3.4, Register Settings.
Bit 2: SINV
0
1
Description
SCTDR1 contents are transmitted as they are
Receive data is stored in SCRDR1 as it is
SCTDR1 contents are inverted before being transmitted
Receive data is stored in SCRDR1 in inverted form
(Initial value)
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013