HD6417750RF240DV Datasheet, PDF (607/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 14 Direct Memory Access Controller (DMAC)
14.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)
Bit:
Initial value:
R/W:
31
SSA2
0
R/W
30
SSA1
0
R/W
29
SSA0
0
R/W
28
STC
0
R/W
27
DSA2
0
R/W
26
DSA1
0
R/W
25
DSA0
0
R/W
24
DTC
0
R/W
Bit: 23
22
21
20
19
18
17
16
—
—
—
—
DS
RL
AM
AL
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R/W (R/W) R/W (R/W)
Bit: 15
14
13
12
11
10
9
8
DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
TM
TS2 TS1 TS0
—
IE
TE
DE
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W
R
R/W R/(W) R/W
Note: The TE bit can only be written with 0 after being read as 1, to clear the flag.
The RL, AM, AL, and DS bits may be absent, depending on the channel.
DMA channel control registers 0–3 (CHCR0–CHCR3) are 32-bit readable/writable registers that
specify the operating mode, transfer method, etc., for each channel. Bits 31–28 and 27–24 indicate
the source address and destination address, respectively; these settings are only valid when the
transfer involves the CS5 or CS6 space and the relevant space has been specified as a PCMCIA
interface space. In other cases, these bits should be cleared to 0. For details of the PCMCIA
interface, see section 13.3.7, PCMCIA Interface, in section 13, Bus State Controller (BSC).
In DDT mode, CHCR0 is set according to the DTR format. (The following settings are fixed:
CHCR0 [31:24] = 0, [18:16] = 0, [15:14] = 01, [13:12] = 01, [2] = 0, [1] = 0, [0] = 1)
Bits 18 and 16 are not present in CHCR2 and CHCR3. In CHCR2 and CHCR3, these bits cannot
be modified (a write value of 0 should always be used) and are always read as 0.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 555 of 1076