HD6417750RF240DV Datasheet, PDF (356/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 10 Clock Oscillation Circuits
SH7750, SH7750S, SH7750R Group
Bits 2 to 0—Clock Select 2 to 0 (CKS2–CKS0): These bits select the clock used for the WTCNT
count from eight clocks obtained by dividing the frequency divider 2 input clock*. The overflow
periods shown in the following table are for use of a 33 MHz input clock, with frequency divider 1
off, and PLL circuit 1 on (×6).
Note: * When PLL1 is switched on or off, the clock following the switch is used.
Description
Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Clock Division Ratio
Overflow Period
0
0
0
1/32 (Initial value)
41 μs
1
1/64
82 μs
1
0
1/128
164 μs
1
1/256
328 μs
1
0
0
1/512
656 μs
1
1/1024
1.31 ms
1
0
1/2048
2.62 ms
1
1/4096
5.25 ms
Note: The up-count may not be performed correctly if bits CKS2–CKS0 are modified while the
WDT is running. Always stop the WDT before modifying these bits.
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013