HD6417750RF240DV Datasheet, PDF (879/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 19 Interrupt Controller (INTC)
19.1.3 Pin Configuration
Table 19.1 shows the INTC pin configuration.
Table 19.1 INTC Pins
Pin Name
Nonmaskable interrupt
input pin
Interrupt input pins
Abbreviation
NMI
IRL3–IRL0
I/O
Input
Input
Function
Input of nonmaskable interrupt request
signal
Input of interrupt request signals
(maskable by IMASK in SR)
19.1.4 Register Configuration
The INTC has the registers shown in table 19.2.
Table 19.2 INTC Registers
Name
Initial
Abbreviation R/W Value^*1
Area 7
P4 Address Address
Interrupt control ICR
register
R/W ^*2
H'FFD00000 H'1FD00000
Interrupt priority IPRA
register A
R/W H'0000
H'FFD00004 H'1FD00004
Interrupt priority IPRB
register B
R/W H'0000
H'FFD00008 H'1FD00008
Interrupt priority IPRC
register C
R/W H'0000
H'FFD0000C H'1FD0000C
Interrupt priority IPRD
register D^*3
R/W H'DA74
H'FFD00010 H'1FD00010
Interrupt priority
level setting
register 00^*4
INTPRI00
R/W H'00000000 H'FE080000 H'1E080000
Interrupt source INTREQ00 R
register 00^*4
H'00000000 H'FE080020 H'1E080020
Interrupt mask
register 00^*4
INTMSK00 R/W H'00000300 H'FE080040 H'1E080040
Interrupt mask INTMSKCLR R
—
clear register 00^*4 00
H'FE080060 H'1E080060
Notes: 1. Initialized by a power-on reset or manual reset.
2. H'8000 when the NMI pin is high, H'0000 when the NMI pin is low.
Access
Size
16
16
16
16
16
32
32
32
32
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 827 of 1076