HD6417750RF240DV Datasheet, PDF (808/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
SH7750, SH7750S, SH7750R Group
16.2.12 Line Status Register (SCLSR2)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
— ORER
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R (R/W)*
Note: * Only 0 can be written, to clear the flag.
Bits 15 to 1—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 0—Overrun Error (ORER): Indicates that an overrun error occurred during reception,
causing abnormal termination.
Bit 0: ORER
0
Description
Reception in progress, or reception has ended normally^*1
[Clearing conditions]
• Power-on reset or manual reset
• When 0 is written to ORER after reading ORER = 1
(Initial value)
1
An overrun error occurred during reception^*2
[Setting condition]
When the next serial reception is completed while the receive FIFO is full
Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in
SCSCR2 is cleared to 0.
2. The receive data prior to the overrun error is retained in SCFRDR2, and the data
received subsequently is lost. Serial reception cannot be continued while the ORER flag
is set to 1.
Page 756 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013