HD6417750RF240DV Datasheet, PDF (746/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 15 Serial Communication Interface (SCI)
SH7750, SH7750S, SH7750R Group
Start of reception
Read ORER, PER, and FER flags
in SCSSR1
PER or FER
or ORER = 1?
No
Yes
Error handling
Read RDRF flag in SCSSR1
1. Receive error handling and
break detection: If a receive
error occurs, read the ORER,
PER, and FER flags in
SCSSR1 to identify the error.
After performing the
appropriate error handling,
ensure that the ORER, PER,
and FER flags are all cleared to
0. Reception cannot be
resumed if any of these flags
are set to 1. In the case of a
framing error, a break can be
detected by reading the value
of the RxD pin.
No
RDRF = 1?
Yes
Read receive data in SCRDR1,
and clear RDRF flag
in SCSSR1 to 0
No
All data received?
Yes
Clear RE bit in SCSCR1 to 0
End of reception
2. SCI status check and receive
data read : Read SCSSR1 and
check that RDRF = 1, then read
the receive data in SCRDR1
and clear the RDRF flag to 0.
3. Serial reception continuation
procedure: To continue serial
reception, complete zero-
clearing of the RDRF flag
before the stop bit for the
current frame is received. (The
RDRF flag is cleared
automatically when the direct
memory access controller
(DMAC) is activated by an RXI
interrupt and the SCRDR1
value is read.)
Figure 15.10 Sample Serial Reception Flowchart (1)
Page 694 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013