HD6417750RF240DV Datasheet, PDF (635/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 14 Direct Memory Access Controller (DMAC)
4. Access size permitted for the on-chip peripheral module register that is the transfer
source or transfer destination.
5. When the transfer request is an external request, only channels 0 and 1 can be used.
6. In DDT mode, transfer requests can be accepted for all channels from external devices
capable of DTR format output.
7. See tables 14.8 and 14.9 for the transfer sources and transfer destinations in DMA
transfer by means of an external request.
(a) Normal DMA Mode
Table 14.8 shows the memory interfaces that can be specified for the transfer source and transfer
destination in DMA transfer initiated by an external request supported by this LSI in normal DMA
mode.
Table 14.8 External Request Transfer Sources and Destinations in Normal DMA Mode
Transfer Direction (Settable Memory Interface)
Transfer Source
Transfer Destination
Usable
Address DMAC
Mode Channels
1 Synchronous DRAM
External device with DACK
Single 0, 1
2 External device with DACK
Synchronous DRAM
Single 0, 1
3 SRAM-type, DRAM
External device with DACK
Single 0, 1
4 External device with DACK
SRAM-type, DRAM
Single 0, 1
5 Synchronous DRAM
SRAM-type, MPX, PCMCIA * Dual
0, 1
6 SRAM-type, MPX, PCMCIA * Synchronous DRAM
Dual
0, 1
7 SRAM-type, DRAM, PCMCIA,
SRAM-type, MPX, PCMCIA * Dual
0, 1
MPX
8 SRAM-type, MPX, PCMCIA * SRAM-type, DRAM, PCMCIA,
Dual
0, 1
MPX
"SRAM-type" in the table indicates an SRAM, byte control SRAM, or burst ROM setting.
Notes: Memory interfaces on which transfer is possible in single address mode are SRAM, byte
control SRAM, burst ROM, DRAM, and synchronous DRAM.
When performing dual address mode transfer, make the DACK output setting for the
SRAM, byte control SRAM, burst ROM, PCMCIA, or MPX interface.
* DACK output setting in dual address mode transfer
(b) DDT Mode
Table 14.9 shows the memory interfaces that can be specified for the transfer source and transfer
destination in DMA transfer initiated by an external request supported by this LSI in DDT mode.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 583 of 1076