HD6417750RF240DV Datasheet, PDF (472/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 13 Bus State Controller (BSC)
SH7750, SH7750S, SH7750R Group
13.2.14 Refresh Count Register (RFCR)
The refresh count register (RFCR) is a 10-bit readable/writable counter that counts the number of
refreshes by being incremented each time the RTCOR register and RTCNT counter values match.
If the RFCR register value exceeds the count limit specified by the LMTS bit in the RTCSR
register, the OVF flag is set in the RTCSR register and the RFCR register is cleared.
RFCR is initialized to H'0000 by a power-on reset, but is not initialized, and retains its contents, in
a manual reset and in standby mode.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: —
—
—
—
—
—
R/W R/W
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
13.2.15 Notes on Accessing Refresh Control Registers
When the refresh timer control/status register (RTCSR), refresh timer counter (RTCNT), refresh
time constant register (RTCOR), and refresh count register (RFCR) are written to, a special code
is added to the data to prevent inadvertent rewriting in the event of program runaway, etc. The
following procedures should be used for read/write operations.
Writing to RTCSR, RTCNT, RTCOR, and RFCR: A word transfer instruction must always be
used when writing to RTCSR, RTCNT, RTCOR, or RFCR. A write cannot be performed with a
byte transfer instruction.
When writing to RTCSR, RTCNT, or RTCOR, set B'10100101 in the upper byte and the write
data in the lower byte, as shown in figure 13.5. When writing to RFCR, set B'101001 in the 6 bits
starting from the MSB in the upper byte, and the write data in the remaining bits.
Page 420 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013