HD6417750RF240DV Datasheet, PDF (514/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 13 Bus State Controller (BSC)
SH7750, SH7750S, SH7750R Group
Figure 13.24 shows the timing of the CAS-before-RAS refresh cycle.
The number of RAS assert cycles in the refresh cycle is specified by bits TRAS2–TRAS0 in
MCR. The specification of the RAS precharge time in the refresh cycle is determined by the
setting of bits TRC2–TRC0 in MCR.
TRr1 TRr2 TRr3 TRr4 TRr5 Trc Trc Trc
CKIO
A25–A0
CSn
RD/WR
RAS
CAS
D63–D0
BS
Figure 13.24 DRAM CAS-Before-RAS Refresh Cycle Timing (TRAS = 0, TRC = 1)
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013