HD6417750RF240DV Datasheet, PDF (463/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 13 Bus State Controller (BSC)
Bits 8 to 6—Address-OE/WE Assertion Delay (A6TED2–A6TED0): These bits set the delay
time from address output to OE/WE assertion on the connected PCMCIA interface. The setting of
these bits is selected when the PCMCIA interface access TC bit is set to 1.
Bit 8: A6TED2
0
1
Bit 7: A6TED1
0
1
0
1
Bit 6: A6TED0
0
1
0
1
0
1
0
1
Waits Inserted
0 (Initial value)
1
2
3
6
9
12
15
Bits 5 to 3—OE/WE Negation-Address Delay (A5TEH2–A5TEH0): These bits set the address
hold delay time from OE/WE negation in a write on the connected PCMCIA interface or in an I/O
card read. The setting of these bits is selected when the PCMCIA interface access TC bit is cleared
to 0.
Bit 5: A5TEH2
0
1
Bit 4: A5TEH1
0
1
0
1
Bit 3: A5TEH0
0
1
0
1
0
1
0
1
Waits Inserted
0 (Initial value)
1
2
3
6
9
12
15
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 411 of 1076