HD6417750RF240DV Datasheet, PDF (22/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

14.4.1 Examples of Transfer between External Memory and an External Device
with DACK........................................................................................................... 602
14.5 On-Demand Data Transfer Mode (DDT Mode) ................................................................ 603
14.5.1 Operation .............................................................................................................. 603
14.5.2 Pins in DDT Mode................................................................................................ 605
14.5.3 Transfer Request Acceptance on Each Channel ................................................... 608
14.5.4 Notes on Use of DDT Module .............................................................................. 631
14.6 Configuration of the DMAC (SH7750R)........................................................................... 634
14.6.1 Block Diagram of the DMAC............................................................................... 634
14.6.2 Pin Configuration (SH7750R) .............................................................................. 636
14.6.3 Register Configuration (SH7750R) ...................................................................... 637
14.7 Register Descriptions (SH7750R)...................................................................................... 640
14.7.1 DMA Source Address Registers 0−7 (SAR0−SAR7)........................................... 640
14.7.2 DMA Destination Address Registers 0−7 (DAR0−DAR7) .................................. 640
14.7.3 DMA Transfer Count Registers 0−7 (DMATCR0−DMATCR7) ......................... 641
14.7.4 DMA Channel Control Registers 0−7 (CHCR0−CHCR7) ................................... 641
14.7.5 DMA Operation Register (DMAOR) ................................................................... 645
14.8 Operation (SH7750R) ........................................................................................................ 647
14.8.1 Channel Specification for a Normal DMA Transfer............................................. 647
14.8.2 Channel Specification for DDT-Mode DMA Transfer ......................................... 647
14.8.3 Transfer Channel Notification in DDT Mode....................................................... 648
14.8.4 Clearing Request Queues by DTR Format ........................................................... 649
14.8.5 Interrupt-Request Codes ....................................................................................... 649
14.9 Usage Notes ....................................................................................................................... 652
Section 15 Serial Communication Interface (SCI)............................................ 655
15.1 Overview............................................................................................................................ 655
15.1.1 Features................................................................................................................. 655
15.1.2 Block Diagram...................................................................................................... 657
15.1.3 Pin Configuration.................................................................................................. 658
15.1.4 Register Configuration.......................................................................................... 658
15.2 Register Descriptions......................................................................................................... 659
15.2.1 Receive Shift Register (SCRSR1) ........................................................................ 659
15.2.2 Receive Data Register (SCRDR1) ........................................................................ 660
15.2.3 Transmit Shift Register (SCTSR1) ....................................................................... 660
15.2.4 Transmit Data Register (SCTDR1)....................................................................... 661
15.2.5 erial Mode Register (SCSMR1)............................................................................ 661
15.2.6 Serial Control Register (SCSCR1)........................................................................ 664
15.2.7 Serial Status Register (SCSSR1) .......................................................................... 667
15.2.8 Serial Port Register (SCSPTR1) ........................................................................... 671
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013