HD6417750RF240DV Datasheet, PDF (165/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 4 Caches
4.1.2 Register Configuration
Table 4.4 shows the cache control registers.
Table 4.4 Cache Control Registers
Name
Initial
Abbreviation R/W Value^*1
P4
Address^*2
Area 7
Address^*2
Access
Size
Cache control
register
CCR
R/W H'0000 0000 H'FF00 001C H'1F00 001C 32
Queue address QACR0
control register 0
R/W Undefined H'FF00 0038 H'1F00 0038 32
Queue address QACR1
control register 1
R/W Undefined H'FF00 003C H'1F00 003C 32
Notes: 1. The initial value is the value after a power-on or manual reset.
2. This is the address when using the virtual/physical address space P4 area. The area 7
address is the address used when making an access from physical address space area
7 using the TLB.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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