HD6417750RF240DV Datasheet, PDF (246/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 6 Floating-Point Unit (FPU)
SH7750, SH7750S, SH7750R Group
The FPSCR cause field contains bits corresponding to all of above sources E, V, Z, O, U, and
I, and the FPSCR flag and enable fields contain bits corresponding to sources V, Z, O, U, and
I, but not E. Thus, FPU errors cannot be disabled.
When an exception source occurs, the corresponding bit in the cause field is set to 1, and 1 is
added to the corresponding bit in the flag field. When an exception source does not occur, the
corresponding bit in the cause field is cleared to 0, but the corresponding bit in the flag field
remains unchanged.
• Enable/disable exception handling
The FPU supports enable exception handling and disable exception handling.
Enable exception handling is initiated in the following cases:
⎯ FPU error (E): FPSCR.DN = 0 and a denormalized number is input
⎯ Invalid operation (V): FPSCR.EN.V = 1 and (instruction = FTRV or invalid operation)
⎯ Division by zero (Z): FPSCR.EN.Z = 1 and division with a zero divisor
⎯ Overflow (O): FPSCR.EN.O = 1 and instruction with possibility of operation result
overflow
⎯ Underflow (U): FPSCR.EN.U = 1 and instruction with possibility of operation result
underflow
⎯ Inexact exception (I): FPSCR.EN.I = 1 and instruction with possibility of inexact operation
result
For information on these possibilities, see the individual instruction descriptions in chapter 9
of the SH-4 Software Manual. The particulars differ demanding on the instruction. All
exception events that originate in the FPU are assigned as the same exception event. The
meaning of an exception is determined by software by reading system register FPSCR and
interpreting the information it contains. If no bits are set in the cause field of FPSCR when one
or more of bits O, U, I, and V (in case of FTRV only) are set in the enable field, this indicates
that an actual exception source is not generated. Also, the destination register is not changed
by any enable exception handling operation.
Except for the above, the FPU disables exception handling. In all processing, the bit
corresponding to source V, Z, O, U, or I is set to 1, and disable exception handling is provided
for each exception.
⎯ Invalid operation (V): qNAN is generated as the result.
⎯ Division by zero (Z): Infinity with the same sign as the unrounded value is generated.
Page 194 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013