HD6417750RF240DV Datasheet, PDF (279/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 7 Instruction Set
Table 7.12 Floating-Point Graphics Acceleration Instructions
Instruction
FMOV DRm,XDn
FMOV XDm,DRn
FMOV XDm,XDn
FMOV @Rm,XDn
FMOV @Rm+,XDn
FMOV @(R0,Rm),XDn
FMOV XDm,@Rn
FMOV XDm,@-Rn
FMOV XDm,@(R0,Rn)
FIPR FVm,FVn
FTRV XMTRX,FVn
FRCHG
FSCHG
Operation
DRm → XDn
XDm → DRn
XDm → XDn
(Rm) → XDn
(Rm) → XDn, Rm + 8 → Rm
(R0 + Rm) → XDn
XDm → (Rn)
Rn – 8 → Rn, XDm → (Rn)
XDm → (R0+Rn)
inner_product [FVm, FVn] →
FR[n+3]
transform_vector [XMTRX,
FVn] → FVn
~FPSCR.FR → FPSCR.FR
~FPSCR.SZ → FPSCR.SZ
Instruction Code
Privileged T Bit
1111nnn1mmm01100 —
—
1111nnn0mmm11100 —
—
1111nnn1mmm11100 —
—
1111nnn1mmmm1000 —
—
1111nnn1mmmm1001 —
—
1111nnn1mmmm0110 —
—
1111nnnnmmm11010 —
—
1111nnnnmmm11011 —
—
1111nnnnmmm10111 —
—
1111nnmm11101101 —
—
1111nn0111111101 —
—
1111101111111101 —
—
1111001111111101 —
—
7.4 Usage Notes
7.4.1
Notes on TRAPA Instruction, SLEEP Instruction, and Undefined Instruction
(H'FFFD)
• Incorrect data may be written to the cache when a TRAPA instruction or undefined instruction
code H'FFFD is executed.
• The ITLB hit judgment may be incorrect when a TRAPA instruction or undefined instruction
code H'FFFD is executed, causing a multi-hit exception to occur after re-registration.
• Incorrect data may be written to an FPU-related register or to the MACH or MACL register
when a TRAPA instruction, SLEEP instruction, or undefined instruction code H'FFFD is
executed.
Conditions Under which Problem Occurs
1. Incorrect data may be written to the instruction cache when the following three conditions
occur at the same time.
a. The instruction cache is enabled (CCR.ICE = 1).
b. A TRAPA instruction or undefined instruction code H'FFFD in a cache-enabled area is
executed.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 227 of 1076