HD6417750RF240DV Datasheet, PDF (849/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 17 Smart Card Interface
When performing data transfer using the DMAC, it is essential to set and enable the DMAC
before carrying out SCI settings. For details of the DMAC setting procedures, see section 14,
Direct Memory Access Controller (DMAC).
17.4 Usage Notes
The following points should be noted when using the SCI as a smart card interface.
(1) Receive Data Sampling Timing and Receive Margin
In asynchronous mode, the SCI operates on a base clock with a frequency of 372 times the transfer
rate. In reception, the SCI synchronizes internally with the fall of the start bit, which it samples on
the base clock. Receive data is latched at the rising edge of the 186th base clock pulse. The timing
is shown in figure 17.10.
372 clocks
186 clocks
0
185
371 0
185
371 0
Base clock
Receive data
(RxD)
Synchronization
sampling timing
Start
bit
D0
D1
Data sampling
timing
Figure 17.10 Receive Data Sampling Timing in Smart Card Mode
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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