HD6417750RF240DV Datasheet, PDF (510/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 13 Bus State Controller (BSC)
SH7750, SH7750S, SH7750R Group
CKIO
A25–A0
CSn
Tnop
Tc1
Tc2
Tc1
Tc2
Tc1
Tc2
Tc1
Tc2
c0
c1
c2
c3
RD/WR
RAS
CASn
D63–D0
(read)
D63–D0
(write)
End of RAS down mode
d0
d0
d1
d1
d2
d2
d3
d3
BS
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.22 (2) DRAM Burst Bus Cycle, RAS Down Mode Continuation
(Fast Page Mode, RCD = 0, AnW = 0)
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013