HD6417750RF240DV Datasheet, PDF (722/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 15 Serial Communication Interface (SCI)
SH7750, SH7750S, SH7750R Group
Bit 3—Parity Error (PER): Indicates that a parity error occurred during reception with parity
addition in asynchronous mode, causing abnormal termination.
Bit 3: PER
Description
0
Reception in progress, or reception has ended normally^*1 (Initial value)
[Clearing conditions]
• Power-on reset, manual reset, standby mode, or module standby
• When 0 is written to PER after reading PER = 1
1
A parity error occurred during reception^*2
[Setting condition]
When, in reception, the number of 1-bits in the receive data plus the parity
bit does not match the parity setting (even or odd) specified by the O/E bit
in SCSMR1
Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCSCR1
is cleared to 0.
2. If a parity error occurs, the receive data is transferred to SCRDR1 but the RDRF flag is
not set. Serial reception cannot be continued while the PER flag is set to 1.
Bit 2—Transmit End (TEND): Indicates that there is no valid data in SCTDR1 when the last bit
of the transmit character is sent, and transmission has been ended.
The TEND flag is read-only and cannot be modified.
Bit 2: TEND
0
1
Description
Transmission is in progress
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When data is written to SCTDR1 by the DMAC
Transmission has been ended
[Setting conditions]
(Initial value)
• Power-on reset, manual reset, standby mode, or module standby
• When the TE bit in SCSCR1 is 0
• When TDRE = 1 on transmission of the last bit of a 1-byte serial
transmit character
Bit 1—Multiprocessor Bit (MPB)*: This bit is read-only and cannot be written to. The read
value is undefined.
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013