HD6417750RF240DV Datasheet, PDF (262/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 7 Instruction Set
SH7750, SH7750S, SH7750R Group
ADD #1, R0
; T bit is not changed by ADD operation
CMP/EQ R1, R0 ; If R0 = R1, T bit is set to 1
BT TARGET ; Branches to TARGET if T bit = 1 (R0 = R1)
In an RTE delay slot, status register (SR) bits are referenced as follows. In instruction access, the
MD bit is used before modification, and in data access, the MD bit is accessed after modification.
The other bits—S, T, M, Q, FD, BL, and RB—after modification are used for delay slot
instruction execution. The STC and STC.L SR instructions access all SR bits after modification.
Constant Values: An 8-bit constant value can be specified by the instruction code and an
immediate value. 16-bit and 32-bit constant values can be defined as literal constant values in
memory, and can be referenced by a PC-relative load instruction.
MOV.W @(disp, PC), Rn
MOV.L @(disp, PC), Rn
There are no PC-relative load instructions for floating-point operations. However, it is possible to
set 0.0 or 1.0 by using the FLDI0 or FLDI1 instruction on a single-precision floating-point
register.
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Sep 24, 2013