HD6417750RF240DV Datasheet, PDF (320/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 9 Power-Down Modes
SH7750, SH7750S, SH7750R Group
9.2.6 Clock-Stop Clear Register 00 (CLKSTPCLR00) (SH7750R Only)
The clock-stop clear register 00 (CLKSTPCLR00) is a 32-bit write-only register that clears the
corresponding bits of the CLKSTP00 register.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: W W W W W W W W W W W W W W W W
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: W W W W W W W W W W W W W W W W
Bits 31 to 0⎯Clock-Stop Clear: Specify whether or not to clear the corresponding bit of the
clock-stop setting. See section 9.2.5, Clock-Stop Register 00 (CLKSTP00) (SH7750R only), for
the correspondence between the bits and the clocks that are stopped.
Bits 31 to 0
0
1
Description
Does not change the clock-stop setting for the corresponding clock
Clears the clock-stop setting for the corresponding clock
9.3 Sleep Mode
9.3.1 Transition to Sleep Mode
If a SLEEP instruction is executed when the STBY bit in STBCR is cleared to 0, the chip switches
from the program execution state to sleep mode. After execution of the SLEEP instruction, the
CPU halts but its register contents are retained. The on-chip peripheral modules continue to
operate, and the clock continues to be output from the CKIO pin.
In sleep mode, a high-level signal is output at the STATUS1 pin, and a low-level signal at the
STATUS0 pin.
Page 268 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013