HD6417750RF240DV Datasheet, PDF (522/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 13 Bus State Controller (BSC)
SH7750, SH7750S, SH7750R Group
In a synchronous DRAM cycle, the BS signal is asserted for one cycle at the start of the bus cycle.
The access sequence is as follows: in a fill operation in the event of a cache miss, 64-bit boundary
data including the missed data is read first, then 32-byte boundary data including the missed data
is read in wraparound mode.
Single Read: With this LSI, as synchronous DRAM is set to burst read/burst write mode, read
data output continues after the required data has been read. To prevent data collisions, after the
required data is read in Td1, empty read cycles Td2 to Td4 are performed, and this LSI waits for
the end of the synchronous DRAM operation. The BS signal is asserted only in Td1.
When the data width is 64 bits, there are 4 burst transfers in a read. In cache-through and other
DMA read cycles, of cycles Td1 to Td4, BS is asserted and data latched only in the Td1 cycle.
Since such empty cycles increase the memory access time, and tend to reduce program execution
speed and DMA transfer speed, it is important both to avoid unnecessary cache-through area
accesses, and to use a data structure that will allow data to be placed at a 32-byte boundary, and to
be transferred in 32-byte units, when carrying out DMA transfer with synchronous DRAM
specified as the source.
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013