HD6417750RF240DV Datasheet, PDF (414/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 13 Bus State Controller (BSC)
Name
Data enable 5
Signals
I/O
WE5/CAS5/ O
DQM5
Data enable 6
WE6/CAS6/
O
DQM6
Data enable 7
WE7/CAS7/
O
DQM7/REG
Ready
Area 0 MPX
interface
specification/
16-bit I/O
RDY
I
MD6/IOIS16 I
Clock enable
Bus release
request
Bus use
permission
Area 0 bus
width/PCMCIA
card select
CKE
O
BREQ/
I
BSACK
BACK/
O
BSREQ
MD3/CE2A^*1 I/O
MD4/CE2B^*2
Endian switchover/ MD5/RAS2^*3 I/O
row address
strobe
SH7750, SH7750S, SH7750R Group
Description
When setting synchronous DRAM interface:
selection signal for D47–D40
When setting DRAM interface: CAS signal for
D47–D40
When setting MPX interface: high-level output
In other cases: write strobe signal for D47–D40
When setting synchronous DRAM interface:
selection signal for D55–D48
When setting DRAM interface: CAS signal for
D55–D48
When setting MPX interface: high-level output
In other cases: write strobe signal for D55–D48
When setting synchronous DRAM interface:
selection signal for D63–D56
When setting DRAM interface: CAS signal for
D63–D56
When setting PCMCIA interface: REG signal
When setting MPX interface: high-level output
In other cases: write strobe signal for D63–D56
Wait state request signal
In power-on reset: Designates area 0 bus as MPX
interface (1: SRAM, 0: MPX)
When setting PCMCIA interface: 16-bit I/O
designation signal. Valid only in little-endian mode.
Synchronous DRAM clock enable control signal
Bus release request signal/bus acknowledge signal
Bus use permission signal/bus request
In power-on reset^*4: external space area 0 bus
width specification signal
When setting PCMCIA interface: CE2A, CE2B
Endian specification in a power-on reset.^*4
RAS2 when DRAM is connected to area 2
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013