HD6417750RF240DV Datasheet, PDF (936/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 21 High-performance User Debug Interface (H-UDI)
SH7750, SH7750S, SH7750R Group
Bits 11 to 0—Reserved: These bits are always read as 1, and should only be written with 1.
SH7750R:
Bit: 15
14
13
12
11
10
9
8
TI7
TI6
TI5
TI4
TI3
TI2
TI1
TI0
Initial value: 1
1
1
1
1
1
1
1
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value: 1
1
1
1
1
1
1
1
R/W: R
R
R
R
R
R
R
R
Bits 15 to 8—Test Instruction Bits (TI7–TI0)
Bit 15: Bit 14: Bit 13: Bit 12: Bit 11: Bit 10: Bit 9:
TI7 TI6 TI5 TI4 TI3 TI2 TI1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
—
—
—
0
1
1
1
—
—
—
1
0
1
—
—
—
—
1
1
1
1
1
1
1
Other than above
Bit 8:
TI0
0
0
—
—
—
1
Description
EXTEST
SAMPLE/PRELOAD
H-UDI reset negate
H-UDI reset assert
H-UDI interrupt
Bypass mode (Initial value)
Reserved
Bits 7 to 0—Reserved: These bits are always read as 1, and should only be written with 1.
Page 884 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013