HD6417750RF240DV Datasheet, PDF (738/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 15 Serial Communication Interface (SCI)
SH7750, SH7750S, SH7750R Group
Table 15.9 SCSMR1 and SCSCR1 Settings for SCI Clock Source Selection
SCSMR1
Bit 7:
C/A
0
1
SCSCR1 Setting
Bit 1:
CKE1
Bit 0:
CKE0
0
0
1
1
0
1
0
0
1
1
0
1
Mode
Asynchronous
mode
SCI Transmit/Receive Clock
Clock
Source SCK Pin Function
Internal SCI does not use SCK pin
Outputs clock with same
frequency as bit rate
External Inputs clock with frequency of
16 times the bit rate
Synchronous
mode
Internal Outputs serial clock
External Inputs serial clock
15.3.2 Operation in Asynchronous Mode
In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the
start of communication and followed by one or two stop bits indicating the end of communication.
Serial communication is thus carried out with synchronization established on a character-by-
character basis.
Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex
communication. Both the transmitter and the receiver also have a double-buffered structure, so
that data can be read or written during transmission or reception, enabling continuous data
transfer.
Figure 15.5 shows the general format for asynchronous serial communication.
In asynchronous serial communication, the transmission line is usually held in the mark state (high
level). The SCI monitors the transmission line, and when it goes to the space state (low level),
recognizes a start bit and starts serial communication.
One serial communication character consists of a start bit (low level), followed by data (in LSB-
first order), a parity bit (high or low level), and finally one or two stop bits (high level).
In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in
reception. The SCI samples the data on the eighth pulse of a clock with a frequency of 16 times
the length of one bit, so that the transfer data is latched at the center of each bit.
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013