HD6417750RF240DV Datasheet, PDF (1123/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Index
Index
A
Address Space........................................... 79
B
Bus Arbitration ....................................... 536
Bus State Controller................................ 357
Address Multiplexing ......................... 451
Areas........................................... 365, 433
Burst Access ....................................... 454
Burst ROM Interface .......................... 497
Byte Control SRAM Interface ............ 529
DRAM Interface ................................. 447
EDO Mode.......................................... 455
Endian................................................. 421
I/O card interface ........................ 368, 500
IC memory card interface ........... 368, 500
Master Mode....................................... 539
MPX Interface .................................... 511
Partial-Sharing Master Mode.............. 541
PCMCIA Interface.............................. 500
PCMCIA Support ............................... 368
RAS Down Mode ............................... 456
Refresh Timing ................................... 461
Refreshing........................................... 484
Slave Mode ......................................... 540
SRAM Interface.................................. 438
Synchronous DRAM Interface ........... 465
Wait State Control .............................. 453
Waits between Access Cycles............. 534
C
Caches..................................................... 111
Address Array............. 131, 133, 137, 139
cache fill ............................................. 125
Data Array .................. 132, 135, 138, 141
IC Index Mode .................................... 131
Instruction Cache ................ 111, 112, 128
OC Index Mode................................... 124
Operand Cache.................... 111, 112, 116
prefetch ............................................... 143
Prefetch Operation .............................. 125
RAM Mode ......................................... 123
Store Queues ....................................... 142
Tag .............................................. 119, 129
U bit .................................................... 119
V bit ............................................ 119, 129
Write-Back Buffer .............................. 122
Write-Through Buffer ......................... 122
Clock Oscillation Circuits....................... 287
Bus Clock Division Ratio ................... 299
Changing the Frequency ..................... 298
Clock Operating Modes ...................... 293
PLL Circuit ......................................... 298
clock pulse generator .............................. 287
Control Registers ................................ 54, 62
DBR ...................................................... 63
Debug base register............................... 63
GBR ...................................................... 63
Global base register............................... 63
Saved general register 15 ...................... 63
Saved program counter ......................... 63
Saved status register.............................. 63
SGR....................................................... 63
SPC ....................................................... 63
SR ......................................................... 62
SSR ....................................................... 63
Status register........................................ 62
VBR ...................................................... 63
Vector base register............................... 63
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 1071 of 1076