HD6417750RF240DV Datasheet, PDF (206/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 5 Exceptions
SH7750, SH7750S, SH7750R Group
Exception Execution
Category Mode
Exception
Priority Priority Vector
Level Order Address
Exception
Offset Code
Interrupt Completion Peripheral DMAC DMTE0 4
type
module
interrupt
DMTE1
(module/
DMTE2
source)
DMTE3
*²
(VBR)
H'600
H'640
H'660
H'680
H'6A0
DMTE4^*3
H'780
DMTE5^*3
H'7A0
DMTE6^*3
H'7C0
DMTE7^*3
H'7E0
DMAE
H'6C0
SCIF ERI
H'700
RXI
H'720
BRI
H'740
TXI
H'760
Priority: Priority is first assigned by priority level, then by priority order within each level (the lowest
number represents the highest priority).
Exception transition destination: Control passes to H'A000 0000 in a reset, and to [VBR + offset] in
other cases.
Exception code: Stored in EXPEVT for a reset or general exception, and in INTEVT for an interrupt.
IRL: Interrupt request level (pins IRL3–IRL0).
Module/source: See the sections on the relevant peripheral modules.
Notes: 1. When BRCR.UBDE = 1, PC = DBR. In other cases, PC = VBR + H'100.
2. The priority order of external interrupts and peripheral module interrupts can be set by
software.
3. SH7750R only.
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013