HD6417750RF240DV Datasheet, PDF (30/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 4 Caches
Figure 4.1 Cache and Store Queue Control Registers ................................................................ 114
Figure 4.2 Configuration of Operand Cache (SH7750, SH7750S)............................................. 117
Figure 4.3 Configuration of Operand Cache (SH7750R) ........................................................... 118
Figure 4.4 Configuration of Write-Back Buffer ......................................................................... 122
Figure 4.5 Configuration of Write-Through Buffer.................................................................... 122
Figure 4.6 Configuration of Instruction Cache (SH7750, SH7750S) ......................................... 128
Figure 4.7 Configuration of Instruction Cache (SH7750R)........................................................ 129
Figure 4.8 Memory-Mapped IC Address Array ......................................................................... 132
Figure 4.9 Memory-Mapped IC Data Array ............................................................................... 133
Figure 4.10 Memory-Mapped OC Address Array ...................................................................... 134
Figure 4.11 Memory-Mapped OC Data Array ........................................................................... 135
Figure 4.12 Memory-Mapped IC Address Array ....................................................................... 138
Figure 4.13 Memory-Mapped IC Data Array ............................................................................. 139
Figure 4.14 Memory-Mapped OC Address Array ...................................................................... 140
Figure 4.15 Memory-Mapped OC Data Array ........................................................................... 141
Figure 4.16 Store Queue Configuration...................................................................................... 143
Section 5 Exceptions
Figure 5.1 Register Bit Configurations....................................................................................... 150
Figure 5.2 Instruction Execution and Exception Handling......................................................... 155
Figure 5.3 Example of General Exception Acceptance Order.................................................... 157
Section 6 Floating-Point Unit (FPU)
Figure 6.1 Format of Single-Precision Floating-Point Number.................................................. 185
Figure 6.2 Format of Double-Precision Floating-Point Number ................................................ 186
Figure 6.3 Single-Precision NaN Bit Pattern.............................................................................. 188
Figure 6.4 Floating-Point Registers ............................................................................................ 190
Section 8 Pipelining
Figure 8.1 Basic Pipelines .......................................................................................................... 232
Figure 8.2 Instruction Execution Patterns................................................................................... 233
Figure 8.3 Examples of Pipelined Execution.............................................................................. 245
Section 9 Power-Down Modes
Figure 9.1 STATUS Output in Power-On Reset ........................................................................ 276
Figure 9.2 STATUS Output in Manual Reset............................................................................. 276
Figure 9.3 STATUS Output in Standby → Interrupt Sequence.................................................. 277
Figure 9.4 STATUS Output in Standby → Power-On Reset Sequence ..................................... 277
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013