HD6417750RF240DV Datasheet, PDF (924/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 20 User Break Controller (UBC)
SH7750, SH7750S, SH7750R Group
in the case of contention between a TRAPA instruction and a post-execution break, the user
break is suppressed. However, in this case, the CMF bit is set by the occurrence of the break
condition.
20.4 User Break Debug Support Function
The user break debug support function enables the processing used in the event of a user break
exception to be changed. When a user break exception occurs, if the UBDE bit is set to 1 in the
BRCR register, the DBR register value will be used as the branch destination address instead of
[VBR + offset]. The value of R15 is saved in the SGR register regardless of the value of the
UBDE bit in the BRCR register or the kind of exception event. A flowchart of the user break
debug support function is shown in figure 20.2.
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013