HD6417750RF240DV Datasheet, PDF (42/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Figure 22.57 MPX Bus Cycle: Burst Read (1) 1st Data (One Internal Wait),
2nd to 8th Data (One Internal Wait) (2) 1st Data (One Internal Wait),
2nd to 4th Data (One Internal Wait + One External Wait) .................................... 999
Figure 22.58 MPX Bus Cycle: Burst Write (1) No Internal Wait (2) 1st Data (One Internal Wait),
2nd to 4th Data (No Internal Wait + External Wait Control) .............................. 1000
Figure 22.59 Memory Byte Control SRAM Bus Cycles (1) Basic Read Cycle (No Wait)
(2) Basic Read Cycle (One Internal Wait) (3) Basic Read Cycle
(One Internal Wait + One External Wait)............................................................ 1001
Figure 22.60 Memory Byte Control SRAM Bus Cycle: Basic Read Cycle
(No Wait, Address Setup/Hold Time Insertion, AnS[0] = 1, AnH[1:0] =0 1)..... 1002
Figure 22.61 TCLK Input Timing ............................................................................................ 1011
Figure 22.62 RTC Oscillation Settling Time at Power-On....................................................... 1011
Figure 22.63 SCK Input Clock Timing .................................................................................... 1011
Figure 22.64 SCI I/O Synchronous Mode Clock Timing ......................................................... 1012
Figure 22.65 I/O Port Input/Output Timing.............................................................................. 1012
Figure 22.66 (a) DREQ/DRAK Timing ................................................................................... 1012
Figure 22.66 (b) DBREQ/TR Input Timing and BAVL Output Timing .................................. 1013
Figure 22.67 TCK Input Timing............................................................................................... 1013
Figure 22.68 RESET Hold Timing........................................................................................... 1014
Figure 22.69 H-UDI Data Transfer Timing.............................................................................. 1014
Figure 22.70 Pin Break Timing ................................................................................................ 1014
Figure 22.71 NMI Input Timing............................................................................................... 1014
Figure 22.72 Output Load Circuit ............................................................................................ 1015
Figure 22.73 Load Capacitance vs. Delay Time....................................................................... 1016
Appendix B Package Dimensions
Figure B.1 Package Dimensions (256-Pin BGA: Devices Other than HD6417750RBA240HV
and HD6417750SBA200V) ................................................................................... 1023
Figure B.2 Package Dimensions (208-Pin QFP) ...................................................................... 1024
Figure B.3 Package Dimensions (264-Pin CSP)....................................................................... 1025
Figure B.4 Package Dimensions (292-Pin BGA) ..................................................................... 1026
Figure B.5 Package Dimensions (256-Pin BGA: HD6417750RBA240HV and
HD6417750SBA200V) .......................................................................................... 1027
Appendix D CKIO2ENB Pin Configuration
Figure D.1 CKIO2ENB Pin Configuration............................................................................... 1033
Appendix G Prefetching of Instructions and its Side Effects
Figure G.1 Instruction Prefetch ................................................................................................ 1061
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Sep 24, 2013