HD6417750RF240DV Datasheet, PDF (270/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 7 Instruction Set
SH7750, SH7750S, SH7750R Group
Table 7.4 Arithmetic Operation Instructions
Instruction
ADD
Rm,Rn
ADD
#imm,Rn
ADDC Rm,Rn
ADDV
Rm,Rn
CMP/EQ #imm,R0
CMP/EQ Rm,Rn
CMP/HS Rm,Rn
CMP/GE Rm,Rn
CMP/HI Rm,Rn
CMP/GT Rm,Rn
CMP/PZ Rn
CMP/PL Rn
CMP/STR Rm,Rn
DIV1
Rm,Rn
DIV0S Rm,Rn
DIV0U
DMULS.L Rm,Rn
DMULU.L Rm,Rn
DT
Rn
Operation
Instruction Code
Privileged T Bit
Rn + Rm → Rn
0011nnnnmmmm1100 —
—
Rn + imm → Rn
0111nnnniiiiiiii —
—
Rn + Rm + T → Rn, carry → T 0011nnnnmmmm1110 —
Carry
Rn + Rm → Rn, overflow → T 0011nnnnmmmm1111 —
Overflow
When R0 = imm, 1 → T
Otherwise, 0 → T
10001000iiiiiiii —
Comparison
result
When Rn = Rm, 1 → T
Otherwise, 0 → T
0011nnnnmmmm0000 —
Comparison
result
When Rn ≥ Rm (unsigned),
1→T
Otherwise, 0 → T
0011nnnnmmmm0010 —
Comparison
result
When Rn ≥ Rm (signed), 1 → T 0011nnnnmmmm0011 —
Otherwise, 0 → T
Comparison
result
When Rn > Rm (unsigned),
1→T
Otherwise, 0 → T
0011nnnnmmmm0110 —
Comparison
result
When Rn > Rm (signed), 1 → T 0011nnnnmmmm0111 —
Otherwise, 0 → T
Comparison
result
When Rn ≥ 0, 1 → T
Otherwise, 0 → T
0100nnnn00010001 —
Comparison
result
When Rn > 0, 1 → T
Otherwise, 0 → T
0100nnnn00010101 —
Comparison
result
When any bytes are equal,
1→T
Otherwise, 0 → T
0010nnnnmmmm1100 —
Comparison
result
1-step division (Rn ÷ Rm)
0011nnnnmmmm0100 —
Calculation
result
MSB of Rn → Q,
MSB of Rm → M, M^Q → T
0010nnnnmmmm0111 —
Calculation
result
0 → M/Q/T
0000000000011001 —
0
Signed, Rn × Rm → MAC,
0011nnnnmmmm1101 —
—
32 × 32 → 64 bits
Unsigned, Rn × Rm → MAC, 0011nnnnmmmm0101 —
—
32 × 32 → 64 bits
Rn – 1 → Rn; when Rn = 0,
1→T
When Rn ≠ 0, 0 → T
0100nnnn00010000 —
Comparison
result
Page 218 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013