HD6417750RF240DV Datasheet, PDF (888/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 19 Interrupt Controller (INTC)
SH7750, SH7750S, SH7750R Group
IPRD (SH7750S and SH7750R only)
Bit: 15
14
13
12
11
10
9
8
Initial value: 1
1
0
1
1
0
1
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
1
1
1
0
1
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 19.6 shows the relationship between the interrupt request sources and the IPRA–IPRD
register bits.
Table 19.6 Interrupt Request Sources and IPRA–IPRD Registers
Bits
Register
15–12
11–8
7–4
3–0
Interrupt priority register A
Interrupt priority register B
TMU0
WDT
TMU1
REF^*1
TMU2
SCI
RTC
Reserved^*2
Interrupt priority register C
Interrupt priority register D^*3
GPIO
IRL0
DMAC
IRL1
SCIF
IRL2
H-UDI
IRL3
Notes: 1. REF is the memory refresh unit in the bus state controller (BSC). See section 13, Bus
State Controller (BSC), for details.
2. Reserved bits: These bits are always read as 0 and should always be written with 0.
3. SH7750S and SH7750R only
As shown in table 19.6, four on-chip peripheral modules are assigned to each register. Interrupt
priority levels are established by setting a value from H'F (1111) to H'0 (0000) in each of the four-
bit groups: 15–12, 11–8, 7–4, and 3–0. Setting H'F designates priority level 15 (the highest level),
and setting H'0 designates priority level 0 (requests are masked).
Page 836 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013