HD6417750RF240DV Datasheet, PDF (408/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 12 Timer Unit (TMU)
SH7750, SH7750S, SH7750R Group
12.5.2 Underflow Flag Writes (SH7750 only)
If 1 is written to the UNF bit in TCR when the UNF bit is already set to 1, the UNF bit may be
cleared to 0.
The following workarounds can be used to avoid this problem.
1. Stopping channel counter operation
Use steps (i) to (iii) below to write 1 to UNF.
(i) Stop counter operation for the channel used to write to UNF.
(ii) Disable the DMAC channels used to access peripheral modules.
(iii) While SR.BL is set to 1, write (the same value as that written to TCR and using the same
access size (word)) to address H'FFD80080, then write 1 to UNF with the next instruction.
2. Not stopping channel counter operation
Make sure to write 0 to UNF. If it is necessary to monitor for underflows, use software to read
TCNT before and after writing to UNF and determine if an underflow has occurred.
12.5.3 TCNT Register Reads
When performing a TCNT register read, processing for synchronization with the timer count
operation is performed. If a timer count operation and register read processing are performed
simultaneously, the TCNT counter value prior to the count-down operation is read by means of the
synchronization processing.
12.5.4 Resetting the RTC Frequency Divider
When the on-chip RTC output clock is selected as the count clock, the RTC frequency divider
should be reset.
12.5.5 External Clock Frequency
Ensure that the external clock frequency for any channel does not exceed Pck/8.
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013