HD6417750RF240DV Datasheet, PDF (530/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 13 Bus State Controller (BSC)
SH7750, SH7750S, SH7750R Group
CKIO
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
D63–D0
(read)
Tpr Tpc Tr Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4
Row
Row
H/L
Row
c1
c1
c2
c3
c4
BS
CKE
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.34 Burst Read Timing (RAS Down, Different Row Addresses)
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013