HD6417750RF240DV Datasheet, PDF (504/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 13 Bus State Controller (BSC)
SH7750, SH7750S, SH7750R Group
Basic Timing: The basic timing for DRAM access is 4 cycles. This basic timing is shown in
figure 13.17. Tpc is the precharge cycle, Tr the RAS assert cycle, Tc1 the CAS assert cycle, and
Tc2 the read data latch cycle.
Tr1
Tr2
Tc1
Tc2
Tpc
CKIO
A25–A0
Row
Column
CSn
RD/WR
RAS
CAS
D63–D0
(read)
D63–D0
(write)
BS
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
Legend:
IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
The DACK is in the high-active setting
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.17 Basic DRAM Access Timing
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013