HD6417750RF240DV Datasheet, PDF (347/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 10 Clock Oscillation Circuits
10.4 CPG Register Description
10.4.1 Frequency Control Register (FRQCR)
The frequency control register (FRQCR) is a 16-bit readable/writable register that specifies
use/non-use of clock output from the CKIO pin, PLL circuit 1 and 2 on/off control, and the CPU
clock, bus clock, and peripheral module clock frequency division ratios. Only word access can be
used on FRQCR.
FRQCR is initialized only by a power-on reset via the RESET pin. The initial value of each bit is
determined by the clock operating mode.
Bit: 15
14
13
—
—
—
Initial value: 0
0
0
R/W: R/W R/W R/W
12
11
10
9
8
— CKOEN PLL1EN PLL2EN IFC2
0
1
1
1
—
R
R/W R/W R/W R/W
Bit:
Initial value:
R/W:
7
IFC1
—
R/W
6
IFC0
—
R/W
5
BFC2
—
R/W
4
BFC1
—
R/W
3
BFC0
—
R/W
2
PFC2
—
R/W
1
PFC1
—
R/W
0
PFC0
—
R/W
Bits 15 to 12—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 11—Clock Output Enable (CKOEN): Specifies whether a clock is output from the CKIO
pin or the CKIO pin is placed in the high-impedance state. When the CKIO pin goes to the high-
impedance state, operation continues at the operating frequency before this state was entered.
When the CKIO pin becomes high-impedance, it is pulled up.
Bit 11: CKOEN
Description
0
CKIO pin goes to high-impedance state (pulled up*)
1
Clock is output from CKIO pin
Note: * It is not pulled up in hardware standby mode.
(Initial value)
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
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