HD6417750RF240DV Datasheet, PDF (402/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 12 Timer Unit (TMU)
SH7750, SH7750S, SH7750R Group
12.2.7 Input Capture Register 2 (TCPR2)
TCPR2 is a 32-bit read-only register for use with the input capture function, provided only in
channel 2.
The input capture function is controlled by means of the input capture control bits (ICPE) and
clock edge bits (CKEG) in TCR2. When input capture occurs, the TCNT2 value is copied into
TCPR2. The value is set in TCPR2 only when the ICPF bit in TCR2 is 0.
TCPR2 is not initialized by a power-on or manual reset, or in standby mode.
Bit: 31
30
29
2
1
0
·············
Initial value:
Undefined
R/W: R
R
R
R
R
R
12.3 Operation
Each channel has a 32-bit timer counter (TCNT) that performs count-down operations, and a 32-
bit timer constant register (TCOR). The channels have an auto-reload function that allows cyclic
count operations, and can also perform external event counting. Channel 2 also has an input
capture function.
12.3.1 Counter Operation
When one of bits STR0–STR4 is set to 1 in the timer start register (TSTR, TSTR2), the timer
counter (TCNT) for the corresponding channel starts counting. When TCNT underflows, the UNF
flag is set in the corresponding timer control register (TCR). If the UNIE bit in TCR is set to 1 at
this time, an interrupt request is sent to the CPU. At the same time, the value is copied from
TCOR into TCNT, and the count-down continues (auto-reload function).
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013