HD6417750RF240DV Datasheet, PDF (625/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 14 Direct Memory Access Controller (DMAC)
When a DMA transfer corresponding to a transfer request signal from an on-chip peripheral
module shown in table 14.5 is carried out, the signal is discontinued automatically. This occurs
every transfer in cycle steal mode, and in the last transfer in burst mode.
14.3.3 Channel Priorities
If the DMAC receives simultaneous transfer requests on two or more channels, it selects a channel
according to a predetermined priority system, either in a fixed mode or round robin mode. The
mode is selected with priority bits PR1 and PR0 in the DMA operation register (DMAOR).
Fixed Mode: In this mode, the relative channel priorities remain fixed. The following priority
orders are available in fixed mode:
• CH0 > CH1 > CH2 > CH3
• CH0 > CH2 > CH3 > CH1
• CH2 > CH0 > CH1 > CH3
The priority order is selected with bits PR1 and PR0 in DMAOR.
Round Robin Mode: In round robin mode, each time the transfer of one transfer unit (byte, word,
longword, quadword, or 32 bytes) ends on a given channel, that channel is assigned the lowest
priority level. This is illustrated in figure 14.3. The order of priority in round robin mode
immediately after a reset is CH0 > CH1 > CH2 > CH3.
Note: In round robin mode, if no transfer request is accepted for any channel during DMA
transfer, the priority order becomes CH0 > CH1 > CH2 > CH3.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 573 of 1076