HD6417750RF240DV Datasheet, PDF (543/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 13 Bus State Controller (BSC)
CKIO
TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 TMw5
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
D63–D0
CKE
(High)
Figure 13.42 (2) Synchronous DRAM Mode Write Timing (Mode Register Set)
Notes on Changing the Burst Length (SH7750R Only): In the SH7750R, when synchronous
DRAM is connected with a 32-bit memory bus, the burst length can be selected as either 4 or 8 by
the setting of the SDBL bit of the BCR3 register. For more details, see the description of the
BCR3 register.
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 491 of 1076