HD6417750RF240DV Datasheet, PDF (887/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 19 Interrupt Controller (INTC)
RCMI: Compare-match interrupt
ROVI: Refresh counter overflow interrupt
H-UDI: High-performance use debug interface
GPIOI: I/O port interrupt
DMTE0–DMTE7: DMAC transfer end interrupts
DMAE: DMAC address error interrupt
Notes: 1. Interrupt priority levels can only be changed in the SH7750S or SH7750R. In the
SH7750, the initial values cannot be changed.
2. SH7750R only
19.3 Register Descriptions
19.3.1 Interrupt Priority Registers A to D (IPRA–IPRD)
Interrupt priority registers A to D (IPRA–IPRD) are 16-bit readable/writable registers that set
priority levels from 0 to 15 for on-chip peripheral module interrupts. IPRA to IPRC are initialized
to H'0000 and IPRD is to H'DA74 by a reset. They are not initialized in standby mode.
IPRA to IPRC
Bit: 15
14
13
12
11
10
9
8
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 835 of 1076