HD6417750RF240DV Datasheet, PDF (1055/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

SH7750, SH7750S, SH7750R Group
Section 22 Electrical Characteristics
22.3.4 Peripheral Module Signal Timing
Table 22.37 Peripheral Module Signal Timing (1)
HD6417750
RBP240 (V)
HD6417750
RBG240 (V)
HD6417750
RBA240HV
*²
Module Item
Symbol Min Max
TMU, Timer clock t
4
—
TCLKWH
RTC
pulse width
(high)
Timer clock
pulse width
(low)
Timer clock
rise time
t
TCLKWL
t_TCLKr
4
—
— 0.8
Timer clock t
TCLKf
fall time
Oscillation
t_ROSC
settling time
— 0.8
—3
SCI
Input clock t
Scyc
cycle (asyn-
chronous)
4
—
Input clock
t_Scyc
cycle (syn-
chronous)
Input clock
t_SCKW
pulse width
6
—
0.4 0.6
Input clock
t_SCKr
rise time
Input clock t
SCKf
fall time
Transfer data t
TXD
delay time
— 0.8
— 0.8
1.5 5.3
Receive data t
RXS
setup time
(synchronous)
16 —
I/O
ports
Receive data t
RXH
hold time
(synchronous)
Output data
delay time
t_PORTD
16 —
1.5 5.3
Input data
setup time
Input data
hold time
t
PORTS
t
PORTH
2
—
1.5 —
HD6417750
RBP200 (V)
HD6417750R
BG200 (V)
HD6417750
RBA240HV*³
*²
Min Max
4
—
HD6417750
F240 (V)
*²
Min Max
4
—
4
—
4
—
— 0.8
— 0.8
—3
4
—
— 0.8
— 0.8
—3
4
—
6
—
6
—
0.4 0.6
— 0.8
— 0.8
1.5 6
16 —
0.4 0.6
— 0.8
— 0.8
1.5 6
16 —
16 —
16 —
1.5 6
2.5 —
1.5 —
1.5 6
3.5 —
1.5 —
HD6417750
RF200 (V)
*²
Min Max Unit Figure
4
— Pcyc^*1 22.61
4
— Pcyc^*1 22.61
— 0.8 Pcyc^*1 22.61
— 0.8 Pcyc^*1 22.61
—3
s
22.62
4
— Pcyc^*1 22.63
6
— Pcyc^*1 22.63
0.4 0.6 t_Scyc
22.63
— 0.8 Pcyc^*1 22.63
— 0.8 Pcyc^*1 22.63
1.5 6
ns
22.64
16 — ns
22.64
16 — ns
22.64
1.5 6
ns
3.5 — ns
1.5 — ns
22.65
22.65
22.65
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013
Page 1003 of 1076