HD6417750RF240DV Datasheet, PDF (456/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 13 Bus State Controller (BSC)
SH7750, SH7750S, SH7750R Group
Bits 17 and 16—RAS-CAS Delay (RCD1, RCD0): When the DRAM interface is set, these bits
set the RAS-CAS assertion delay time. When the synchronous DRAM interface is set, these bits
set the bank active-read/write command delay time.
Bit 17: RCD1
Bit 16: RCD0
DRAM
0
0
2 cycles
1
3 cycles
1
0
4 cycles
1
5 cycles
Note: * Inhibited in RAS down mode.
Description
Synchronous DRAM
Reserved (Setting prohibited)
2 cycles
3 cycles
4 cycles*
Bits 15 to 13—Write Precharge Delay (TRWL2–TRWL0): These bits set the synchronous
DRAM write precharge delay time. In auto-precharge mode, they specify the time until the next
bank active command is issued after a write cycle. After a write cycle, the next active command is
not issued for a period equivalent to the setting values of the TPC[2:0] and TRWL[2:0] bits.*
After a write cycle, the next precharge command is not issued for a period of TRWL. This setting
is valid only when synchronous DRAM interface is set.
Note: * For setting values and the period during which no command is issued, see 22.3.3, Bus
Timing.
Bit 15: TRWL2 Bit 14: TRWL1 Bit 13: TRWL0 Write Precharge ACT Delay Time
0
0
0
1 (Initial value)
1
2
1
0
3*
1
4*
1
0
0
5*
1
Reserved (Setting prohibited)
1
0
Reserved (Setting prohibited)
1
Reserved (Setting prohibited)
Note: * Inhibited in RAS down mode.
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R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013