HD6417750RF240DV Datasheet, PDF (372/1132 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series

Section 11 Realtime Clock (RTC)
SH7750, SH7750S, SH7750R Group
11.2.9 Second Alarm Register (RSECAR)
RSECAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD-coded
second value counter, RSECCNT. When the ENB bit is set to 1, the RSECAR value is compared
with the RSECCNT value. Comparison between the counter and the alarm register is performed
for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in
which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match.
The setting range is decimal 00 to 59 + ENB bit. The RTC will not operate normally if any other
value is set.
The ENB bit in RSECAR is initialized to 0 by a power-on reset. The other fields in RSECAR are
not initialized by a power-on or manual reset, or in standby mode.
Bit:
Initial value:
R/W:
7
ENB
0
R/W
6
5
4
3
2
1
0
10-second units
1-second units
Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R/W R/W R/W R/W R/W R/W R/W
11.2.10 Minute Alarm Register (RMINAR)
RMINAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD-coded
minute value counter, RMINCNT. When the ENB bit is set to 1, the RMINAR value is compared
with the RMINCNT value. Comparison between the counter and the alarm register is performed
for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in
which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match.
The setting range is decimal 00 to 59 + ENB bit. The RTC will not operate normally if any other
value is set.
The ENB bit in RMINAR is initialized by a power-on reset. The other fields in RMINAR are not
initialized by a power-on or manual reset, or in standby mode.
Bit:
Initial value:
R/W:
7
ENB
0
R/W
6
5
4
3
2
1
0
10-minute units
1-minute units
Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R/W R/W R/W R/W R/W R/W R/W
Page 320 of 1076
R01UH0456EJ0702 Rev. 7.02
Sep 24, 2013